Today, when i reported at the office for my internship programme, I was thinking that the office was too simple. But then, after the usual intro with the chief and allotment of project, I could realise that I was wrong. I have been running away from S/W projects all these days and now I get to realise there’s no area without S/W. 🙁 My thesis title is “Higher level testcase synthesis for functional verification” (If you cant understand, don’t worry! I still haven’t got the hold of it) I have to work with Linux,C,Verilog,VHDL and another new S/W (This list is for now.. Yet to discover more.) Anyhow, I have to get on with it!!